研究成果

編號	著作名稱
1	C.-H. Wang and T.-Y. Hsieh, ?quot;On probability of detection lossless concurrent error detection based on implications,?quot; IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, DOI (identifier) 10.1109/TCAD.2017.2740289, pp. 1-14, Aug. 2017.
2	T.-Y. Hsieh, K.-H. Li, and C.-C. Chung, ?quot;A fault-analysis oriented re-design and cost-effectiveness evaluation methodology for error tolerant applications,?quot; Microelectronics Journal, DOI (identifier) 10.1016/j.mejo.2017.05.018, Vol. 66C, pp. 48-57, Jun. 2017.
3	T.-Y. Hsieh, T.-L. Chih, and M.-J. Wu, ?quot;Cost-effective enhancement on both yield and reliability for cache designs based on performance degradation tolerance,?quot; IEEE Transactions on VLSI Systems, Vol. 25, No. 9, pp. 2434-2448, May 2017.
4	T.-Y. Hsieh, Y.-H. Peng and K.-C. Cheng, ?quot;Structural variance based error-tolerability test method for image processing applications,?quot; IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, DOI (identifier) 10.1109/TCAD.2017.2705050, pp. 1-14, May 2017.
5	T.-Y. Hsieh, Y.-H. Peng, K.-C. Cheng and T.-A. Cheng, ?quot;Error-tolerability enhancement via bit inversion and median filtering for single-bit errors in image processing circuits,?quot; Microsystem Technologies, doi:10.1007/s00542-016-3164-0, pp. 1-9, Oct. 2016.
6	T.-Y. Hsieh, T.-P. Wang, S. Yang, C.-A. Hsu and Y.-L. Lin, ?quot;An area-efficient scalable test module to support low pin-count testing,?quot; IEICE Transactions on Electronics, E99-C,3, pp. 404-414, Mar. 2016.
7	T.-Y, Hsieh, C.-H. Wang, T.-L. Chih, and Y.-H. Chi, ?quot;A performance degradation tolerable cache design by exploiting memory hierarchies,?quot; IEEETransactionson VLSI Systems, Vol. 24, No. 2, pp. 784-788, Feb. 2016.
8	T.-Y. Hsieh, C.-H. Wang, C.-W. Kuo, S.-Y. Huang and T.-L. Chih, ?quot;Performance degradation tolerance analysis and design for effective yield enhancement,?quot; Journal of Electronic Testing, Vol. 31, No. 5, pp. 427-441, Dec. 2015.
9	T.-Y. Hsieh, Y.-H. Peng and K.-H. Li, ?quot;Efficient error-tolerability testing on image processing circuits based on equivalent error rate transformation,?quot; Journal of Electronic Testing, Vol. 30, No. 6, pp. 687-699, Dec. 2014.
10	W.-C. Lien, K.-J. Lee, T.-Y. Hsieh and K. Chakrabarty, ?quot;An efficient LFSR reseeding based on internal-response feedback,?quot; Journal of Electronic Testing, Vol. 30, No. 6, pp. 673-685, Dec. 2014.
11	W.-C. Lien, K.-J. Lee, T.-Y. Hsieh and W.-L. Ang, ?quot;Efficient on-chip test generation scheme based on programmable and multiple twisted-ring counters,?quot; IEEETransactionson Computer-Aided Design of Integrated Circuits and Systems, Vol. 32, No. 8, pp. 1254-1264, Aug. 2013.
12	W.-C. Lien, K.-J. Lee, T.-Y. Hsieh, K. Chakrabarty and Y.-H. Wu, ?quot;Counter-based output selection for test response compaction,?quot; IEEETransactionson Computer-Aided Design of Integrated Circuits and Systems, Vol. 32, No. 1, pp. 152-164, Jan. 2013.
13	K.-J. Lee, T.-Y. Hsieh and M. A. Breuer, ?quot;Efficient over-detection elimination of acceptable faults for yield improvement,?quot; IEEETransactionson Computer-Aided Design of Integrated Circuits and Systems, Vol. 31, No. 5, pp. 754-764, May 2012.
14	K.-J. Lee, W.-C. Lien and T.-Y. Hsieh, ?quot;Test response compaction via output bit selection,?quot; IEEETransactionson Computer-Aided Design of Integrated Circuits and Systems, Vol. 30, No. 10, pp. 1534-1544, Oct. 2011.
15	T.-Y. Hsieh, K.-J. Lee and M. A. Breuer, ?quot;An error-tolerance-based test methodology to support product grading for yield enhancement,?quot; IEEETransactionson Computer-Aided Design of Integrated Circuits and Systems, Vol. 30, No. 6, pp. 930-934, Jun. 2011.
16	K.-J. Lee, T.-Y. Hsieh, C.-Y. Chang, Y.-T. Hong and W.-C. Huang, ?quot;On-chip SOC test platform design based on IEEE 1500 standard,?quot; IEEETransactionson VLSI Systems, Vol. 18, No. 7, pp. 1134-1139, Jul. 2010.
17	T.-Y. Hsieh, K.-J. Lee and M. A. Breuer, ?quot;An error rate based test methodology to support error-tolerance,?quot; IEEETransactionson Reliability, Vol. 57, No. 1, pp. 204-214, Mar. 2008.
18	T.-Y. Hsieh, K.-J. Lee and M. A. Breuer, ?quot;Preventing over-detection of acceptable faults for yield enhancement,?quot; Int?#39;l. Journal of Electrical Engineering, Vol. 14, No. 3, pp. 185-193, Jun. 2007.

編號	著作名稱
1	T.-Y. Hsieh, T.-A. Cheng and C.-R. Chen, ?quot;Error-tolerability evaluation and test for images in face detection applications,?quot; IEEE Asian Test Symp., pp. 1-6, Nov. 2017.
2	C.-H. Wang and T.-Y. Hsieh, ?quot;A hybrid concurrent error detection scheme for simultaneous improvement on probability of detection and diagnosability,?quot; IEEE Int?rsquo;l. Test Conference in Asia, pp. 1-6, Sep. 2017.
3	T.-Y. Hsieh, T.-A. Cheng and C.-R. Chen, ?quot;Approximate functional testing for image applications based on error-tolerance,?quot; IEEE Int?rsquo;l. Conference on Consumer Electronics-Taiwan, pp. 203-204, Jun. 2017.
4	T.-Y. Hsieh and T.-A. Cheng, ?quot;On repair of erroneous images for faulty circuits,?quot; IEEEInt?#39;l. Conf. on Applied System Innovation (First Prize Paper Award), pp. 1812-1815, May 2017.
5	T.-Y. Hsieh and Y.-H. Peng, ?quot;A Design-Independent On-Line System Dependability Enhancement Framework Based on Error-Tolerance,?quot; IEEEInt?#39;l. Conf. on Applied System Innovation, pp. 1-4, May 2016.
6	T.-Y. Hsieh and Y.-H. Peng, ?quot;Filtering-based error-tolerability evaluation of image processing circuits,?quot;IEEEInt?#39;l. On-Line Testing Symp., pp. 132-137, Jul. 2015.
7	W.-C. Lien, K.-J. Lee, K. Chakrabarty and T.-Y. Hsieh, ?quot;Output-bit selection with X-avoidance using multiple counters for test-response compaction,?quot; IEEEEuropean Test Symp., pp. 1-6, May 2014.
8	T.-Y. Hsieh, K.-H. Li and Y.-H. Peng, ?quot;On efficient error-tolerability evaluation and maximization for image processing applications,?quot;IEEEInt?#39;l. Symp. on VLSI Design, Automation and Test, Apr. 2014.
9	W.-C. Lien, K.-J. Lee, K. Chakrabarty and T.-Y. Hsieh, ?quot;Output selection for test response compaction based on multiple counters,?quot;IEEEInt?#39;l. Symp. on VLSI Design, Automation and Test, Apr. 2014.
10	W.-C. Lien, K.-J. Lee, T.-Y. Hsieh, K. Chakrabarty, ?quot;A new LFSR reseeding scheme via internal response feedback,?quot; IEEE Asian Test Sym., pp. 97-102, Nov. 2013.
11	T.-Y. Hsieh, Y.-H. Peng and C.-C. Ku, ?quot;An efficient test methodology for image processing applications based on error-tolerance,?quot; IEEE Asian Test Symp., pp. 289-294, Nov. 2013.
12	T.-Y. Hsieh, C.-C. Ku and C.-H. Yeh, ?quot;A yield and reliability enhancement framework for image processing applications,?quot; IEEE Asia Pacific Conference on Circuits and Systems, pp. 683-686, Dec. 2012.
13	W.-C. Lien, K.-J. Lee and T.-Y. Hsieh, ?quot;A test-per-clock LFSR reseeding algorithm for concurrent reduction on test sequence length and test data volume,?quot;IEEEAsian Test Symp., pp. 278-283, Nov. 2012.
14	W.-C Lien, K,-J. Lee and T.-Y. Hsieh, ?quot;Output bit selection for test response compaction based on a single counter,?quot; IEEEInt?rsquo;l. Conf. on Solid-State Integrated Circuit Technology(ICSICT), pp. 1-4, Oct. 2012.
15	W.-C. Lien, K.-J. Lee, T.-Y. Hsieh, S.-S. Chien and K. Chakrabarty, ?quot;Accumulator-based output selection for test response compaction,?quot; IEEEInt?#39;l. Symp. on Circuits and Systems, pp. 2313-2316, May 2012.
16	W.-C. Lien, T.-Y. Hsieh and K.-J. Lee, ?quot;Routing-efficient implementation of an internal-response-based BIST architecture,?quot; IEEEInt?#39;l. Symp. on VLSI Design, Automation and Test, pp. 1-4, Apr. 2012.
17	W.-C. Lien, T.-Y. Hsieh, C.-T. Tsai and K.-J. Lee, ?quot;A rotation-based BIST with self-feedback logic to achieve complete fault coverage,?quot; IEEEInt?#39;l. Symp. on VLSI Design, Automation and Test, pp. 252-255, Apr. 2011.
18	T.-Y. Hsieh, M. A. Breuer, M. Annavaram, S. K. Gupta and K.-J. Lee, ?quot;Tolerance of performance degrading faults for effective yield improvement,?quot;IEEEInt?#39;l. Test Conf., Nov. 2009.
19	T.-Y. Hsieh, K.-J. Lee and M. A. Breuer, ?quot;An efficient multi-phase test technique to perfectly prevent over-detection of acceptable faults for optimal yield improvement via error-tolerance,?quot; IEEEInt?#39;l. Symp. on VLSI Design, Automation and Test, pp. 255-258, Apr. 2009.
20	T.-Y. Hsieh, K.-J. Lee, C.-L. Lu and M. A. Breuer, ?quot;A systematic methodology to employ error-tolerance for yield improvement,?quot; IEEEInt?#39;l. Symp. on VLSI Design, Automation and Test, pp. 105-108, Apr. 2008.
21	T.-Y. Hsieh, K.-J. Lee and J.-J. You, ?quot;Test efficiency analysis and improvement of SOC test platforms,?quot; IEEEAsian Test Symp., pp. 463-466, Oct. 2007.
22	T.-Y. Hsieh, K.-J. Lee and M. A. Breuer, ?quot;Reduction of detected acceptable faults for yield improvement via error-tolerance,?quot; IEEEDesign Automation and Test in Europe Conf. and Exhibition, pp. 1599-1604, Apr. 2007.
23	T.-Y. Hsieh, K.-J. Lee and M. A. Breuer, ?quot;An error-oriented test methodology to improve yield with error-tolerance,?quot; IEEEVLSI Test Symp., pp. 130-135, May 2006.
24	K.-J. Lee, T.-Y. Hsieh, and M. A. Breuer, ?quot;A novel test methodology based on error-rate to support error-tolerance,?quot;IEEEInt?#39;l. Test Conf., pp. 1136-1144, Nov. 2005.